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| author | Yann Herklotz <git@yannherklotz.com> | 2020-06-26 09:40:16 +0100 |
|---|---|---|
| committer | Yann Herklotz <git@yannherklotz.com> | 2020-06-26 09:40:31 +0100 |
| commit | 50ec2fb12454c2bc1f902c955f0b81df71b58c39 (patch) | |
| tree | 8ffd09be682442cedddc6106c242962e614e236c /src/verilog/Verilog.v | |
| parent | cf9949a5151aa9ed86554fb31c2a56fad0614a10 (diff) | |
| download | vericert-kvx-50ec2fb12454c2bc1f902c955f0b81df71b58c39.tar.gz vericert-kvx-50ec2fb12454c2bc1f902c955f0b81df71b58c39.zip | |
Fix Verilog semantics and fix order of always blocks
Diffstat (limited to 'src/verilog/Verilog.v')
| -rw-r--r-- | src/verilog/Verilog.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/verilog/Verilog.v b/src/verilog/Verilog.v index d476710..555ddbd 100644 --- a/src/verilog/Verilog.v +++ b/src/verilog/Verilog.v @@ -712,7 +712,7 @@ Definition empty_stack (m : module) : assocmap_arr := Inductive step : genv -> state -> Events.trace -> state -> Prop := | step_module : - forall asr asa asr' asa' basr1 nasr1 basa1 nasa1 f stval pstval m sf st g, + forall asr asa asr' asa' basr1 nasr1 basa1 nasa1 f stval pstval m sf st g ist, asr!(m.(mod_st)) = Some ist -> valueToPos ist = st -> mis_stepp f (mkassociations asr empty_assocmap) |