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author | Yann Herklotz <git@yannherklotz.com> | 2020-06-22 09:58:18 +0100 |
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committer | Yann Herklotz <git@yannherklotz.com> | 2020-06-22 09:58:32 +0100 |
commit | 9089af0dbd8dc079c16501c73727df82c34c530d (patch) | |
tree | 89f4e7761092dc0dd83532acb1aaaf0c26546563 /src/verilog | |
parent | c02c4c9c4f1e4529526676e5e6aca2b44dd4584c (diff) | |
download | vericert-kvx-9089af0dbd8dc079c16501c73727df82c34c530d.tar.gz vericert-kvx-9089af0dbd8dc079c16501c73727df82c34c530d.zip |
Only print out main as everything is inlined
Diffstat (limited to 'src/verilog')
-rw-r--r-- | src/verilog/PrintVerilog.ml | 18 |
1 files changed, 10 insertions, 8 deletions
diff --git a/src/verilog/PrintVerilog.ml b/src/verilog/PrintVerilog.ml index 2d8af02..5dc0386 100644 --- a/src/verilog/PrintVerilog.ml +++ b/src/verilog/PrintVerilog.ml @@ -188,14 +188,16 @@ let debug_always i clk state = concat [ ] let pprint_module debug i n m = - let inputs = m.mod_start :: m.mod_reset :: m.mod_clk :: m.mod_args in - let outputs = [m.mod_finish; m.mod_return] in - concat [ indent i; "module "; (extern_atom n); - "("; concat (intersperse ", " (List.map register (inputs @ outputs))); ");\n"; - fold_map (pprint_module_item (i+1)) m.mod_body; - if debug then debug_always i m.mod_clk m.mod_st else ""; - indent i; "endmodule\n\n" - ] + if (extern_atom n) = "main" then + let inputs = m.mod_start :: m.mod_reset :: m.mod_clk :: m.mod_args in + let outputs = [m.mod_finish; m.mod_return] in + concat [ indent i; "module "; (extern_atom n); + "("; concat (intersperse ", " (List.map register (inputs @ outputs))); ");\n"; + fold_map (pprint_module_item (i+1)) m.mod_body; + if debug then debug_always i m.mod_clk m.mod_st else ""; + indent i; "endmodule\n\n" + ] + else "" let print_result pp lst = let rec print_result_in pp = function |