diff options
-rw-r--r-- | src/verilog/PrintVerilog.ml | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/src/verilog/PrintVerilog.ml b/src/verilog/PrintVerilog.ml index 5265c97..f8d597a 100644 --- a/src/verilog/PrintVerilog.ml +++ b/src/verilog/PrintVerilog.ml @@ -169,9 +169,12 @@ let testbench = "module testbench; always #5 clk = ~clk; + reg [31:0] count; + initial count = 0; always @(posedge clk) begin + count <= count + 1; if (finish == 1) begin - $display(\"finished: %d\", return_val); + $display(\"finished: %d cycles %d\", return_val, count); $finish; end end |