diff options
| -rw-r--r-- | src/Compiler.v | 2 | ||||
| -rw-r--r-- | src/verilog/PrintVerilog.ml | 5 |
2 files changed, 5 insertions, 2 deletions
diff --git a/src/Compiler.v b/src/Compiler.v index 0a8617d..2ade983 100644 --- a/src/Compiler.v +++ b/src/Compiler.v @@ -85,7 +85,7 @@ Definition transf_backend (r : RTL.program) : res Verilog.program := @@ Tailcall.transf_program @@@ Inlining.transf_program @@ Renumber.transf_program - @@ Constprop.transf_program + (* @@ Constprop.transf_program *) @@ Renumber.transf_program @@@ CSE.transf_program @@@ Deadcode.transf_program diff --git a/src/verilog/PrintVerilog.ml b/src/verilog/PrintVerilog.ml index 7f3eb29..a172b3a 100644 --- a/src/verilog/PrintVerilog.ml +++ b/src/verilog/PrintVerilog.ml @@ -183,9 +183,12 @@ let testbench = "module testbench; always #5 clk = ~clk; + reg [31:0] count; + initial count = 0; always @(posedge clk) begin + count <= count + 1; if (finish == 1) begin - $display(\"finished: %d\", return_val); + $display(\"finished: %d cycles %d\", return_val, count); $finish; end end |