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-rw-r--r--src/hls/PrintVerilog.ml4
1 files changed, 3 insertions, 1 deletions
diff --git a/src/hls/PrintVerilog.ml b/src/hls/PrintVerilog.ml
index 8c9f20e..824623e 100644
--- a/src/hls/PrintVerilog.ml
+++ b/src/hls/PrintVerilog.ml
@@ -257,7 +257,9 @@ let pprint_module debug i n m =
concat [ indent i; "module "; (extern_atom n);
"("; concat (intersperse ", " (List.map register (inputs @ outputs))); ");\n";
fold_map (pprint_module_item (i+1)) m.mod_body;
- concat (List.map (print_funct_units m.mod_clk) m.mod_funct_units);
+ concat (List.map (print_funct_units m.mod_clk)
+ (Maps.PTree.elements m.mod_funct_units.avail_units
+ |> List.map snd));
if !option_initial then print_initial i (Nat.to_int m.mod_stk_len) m.mod_stk else "";
if debug then debug_always_verbose i m.mod_clk m.mod_st else "";
indent i; "endmodule\n\n"