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-rw-r--r--src/hls/Verilog.v2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/hls/Verilog.v b/src/hls/Verilog.v
index c5dab9e..e5f86d5 100644
--- a/src/hls/Verilog.v
+++ b/src/hls/Verilog.v
@@ -149,7 +149,7 @@ Inductive binop : Type :=
(** ** Unary Operators *)
Inductive unop : Type :=
-| Vneg (** negation ([~]) *)
+| Vneg (** negation ([-]) *)
| Vnot. (** not operation [!] *)
(** ** Expressions *)