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-rw-r--r--src/verilog/PrintVerilog.ml6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/verilog/PrintVerilog.ml b/src/verilog/PrintVerilog.ml
index d81bf18..700b8e3 100644
--- a/src/verilog/PrintVerilog.ml
+++ b/src/verilog/PrintVerilog.ml
@@ -180,8 +180,7 @@ let pprint_module i n m =
concat [ indent i; "module "; (extern_atom n);
"("; concat (intersperse ", " (List.map register (inputs @ outputs))); ");\n";
fold_map (pprint_module_item (i+1)) m.mod_body;
- indent i; "endmodule\n\n";
- testbench
+ indent i; "endmodule\n\n"
]
let print_result pp lst =
@@ -201,4 +200,5 @@ let print_globdef pp (id, gd) =
| _ -> ()
let print_program pp prog =
- List.iter (print_globdef pp) prog.prog_defs
+ List.iter (print_globdef pp) prog.prog_defs;
+ pstr pp testbench