| Commit message (Collapse) | Author | Age | Files | Lines | ||
|---|---|---|---|---|---|---|
| ... | ||||||
| | * | Refine the semantics | Yann Herklotz | 2020-05-04 | 3 | -56/+130 | |
| | | | ||||||
| | * | Add code to debug execution of HLSsave/old-step | Yann Herklotz | 2020-05-03 | 3 | -0/+137 | |
| | | | ||||||
| | * | Add proofs and specification of Verilog conversion | Yann Herklotz | 2020-05-03 | 2 | -0/+158 | |
| | | | ||||||
| | * | Add state transition conversion functions | Yann Herklotz | 2020-05-03 | 1 | -2/+14 | |
| | | | ||||||
| | * | Add hex notation to values | Yann Herklotz | 2020-05-03 | 1 | -0/+9 | |
| | | | ||||||
| | * | Change to State | Yann Herklotz | 2020-05-03 | 1 | -21/+22 | |
| | | | ||||||
| | * | Add documentation and conform to specification | Yann Herklotz | 2020-04-29 | 1 | -24/+41 | |
| | | | ||||||
| | * | Add CompCert semantics for Verilog | Yann Herklotz | 2020-04-24 | 1 | -81/+152 | |
| | | | ||||||
| | * | Add valueToInt function | Yann Herklotz | 2020-04-24 | 1 | -0/+3 | |
| | | | ||||||
| | * | Add OS detection to makefile | Yann Herklotz | 2020-04-23 | 2 | -16/+13 | |
| | | | ||||||
| | * | Add stmnt_runp inductive | Yann Herklotz | 2020-04-22 | 1 | -27/+106 | |
| | | | ||||||
| * | | Stop using tuples for register declarations | James Pollard | 2020-05-30 | 1 | -37/+39 | |
| | | | | | | | | | We use a proper record type now. | |||||
| * | | Fix addressing to add support for arbitraty pointer operations | James Pollard | 2020-05-27 | 1 | -10/+19 | |
| | | | | | | | | | | | | | Currently cannot guarantee alignment in some cases (single reg addressing); will need to fix this in order to prove correctness, perhaps by keeping track of alignment from LEA onwards using AbsInt? | |||||
| * | | Bug fix: stack address normalisation | James Pollard | 2020-05-26 | 1 | -1/+1 | |
| | | | ||||||
| * | | (Tentatively) working stack array/memory support. | James Pollard | 2020-05-26 | 3 | -37/+62 | |
| | | | ||||||
| * | | Add pattern matches and plumb through stack reg | James Pollard | 2020-05-25 | 1 | -5/+21 | |
| | | | ||||||
| * | | Start work on array support | James Pollard | 2020-05-25 | 1 | -0/+1 | |
| | | | | | | | | | Try to add a verilog register to represent the stack. | |||||
| * | | Merge pull request #4 from ymherklotz/develop | Yann Herklotz | 2020-04-22 | 12 | -158/+804 | |
| |\| | | | | | Verilog simulation using defined semantics | |||||
| | * | Improve the printing of results | Yann Herklotz | 2020-04-22 | 1 | -4/+5 | |
| | | | ||||||
| | * | Return the actual result of the module | Yann Herklotz | 2020-04-22 | 1 | -2/+5 | |
| | | | ||||||
| | * | Remove unnecessary Lemma | Yann Herklotz | 2020-04-22 | 1 | -8/+1 | |
| | | | | | | | | | | | Still cannot run these functions inside Coq itself, however, they work when they are extracted to Caml. | |||||
| | * | Use State in semantics instead of splitting it up | Yann Herklotz | 2020-04-22 | 1 | -95/+98 | |
| | | | ||||||
| | * | Improve printing of results | Yann Herklotz | 2020-04-22 | 2 | -7/+13 | |
| | | | ||||||
| | * | Merge branch 'master' into develop | Yann Herklotz | 2020-04-19 | 1 | -0/+24 | |
| | |\ | |/ |/| | ||||||
| * | | Add travis url | Yann Herklotz | 2020-04-17 | 1 | -1/+1 | |
| | | | ||||||
| * | | Fix examples for current version of coqup | Yann Herklotz | 2020-04-17 | 1 | -3/+3 | |
| | | | ||||||
| * | | Add information about downloading compcert | Yann Herklotz | 2020-04-17 | 1 | -0/+14 | |
| | | | ||||||
| * | | Add examples on how to run HLS tool | Yann Herklotz | 2020-04-17 | 1 | -0/+10 | |
| | | | ||||||
| * | | [#1 #2] Update README for installation | Yann Herklotz | 2020-04-17 | 1 | -8/+14 | |
| | | | ||||||
| | * | Add travis url | Yann Herklotz | 2020-04-17 | 1 | -1/+1 | |
| | | | ||||||
| | * | Fix Verilog.v | Yann Herklotz | 2020-04-17 | 1 | -1/+1 | |
| | | | ||||||
| | * | Add main module run | Yann Herklotz | 2020-04-17 | 2 | -51/+79 | |
| | | | ||||||
| | * | Fix printing with new Verilog AST | Yann Herklotz | 2020-04-17 | 2 | -26/+54 | |
| | | | ||||||
| | * | Only generate clocked always blocks | Yann Herklotz | 2020-04-17 | 1 | -13/+13 | |
| | | | ||||||
| | * | Extract simulator | Yann Herklotz | 2020-04-17 | 2 | -5/+5 | |
| | | | ||||||
| | * | Update driver to support simulator | Yann Herklotz | 2020-04-17 | 1 | -15/+60 | |
| | | | ||||||
| | * | Add Simulator.v | Yann Herklotz | 2020-04-17 | 2 | -1/+33 | |
| | | | ||||||
| | * | [#1 #2] Update README for installation | Yann Herklotz | 2020-04-17 | 1 | -8/+14 | |
| | | | ||||||
| | * | Add do notation for option | Yann Herklotz | 2020-04-15 | 1 | -0/+11 | |
| | | | ||||||
| | * | Make proofs simpler using auto | Yann Herklotz | 2020-04-15 | 1 | -59/+45 | |
| | | | | | | | | | | | This makes changes to theorems easier, as the proofs will likely not have to be fixed. The runtime is also not much slower. | |||||
| | * | Add Verilog semantics with new Verilog module | Yann Herklotz | 2020-04-15 | 1 | -33/+326 | |
| | | | ||||||
| | * | Create Value module for bitvectors | Yann Herklotz | 2020-04-15 | 1 | -0/+217 | |
| |/ | ||||||
| * | Add proof about state wf | Yann Herklotz | 2020-04-08 | 1 | -40/+193 | |
| | | ||||||
| * | Add partial proof of well formed state | Yann Herklotz | 2020-04-06 | 1 | -24/+136 | |
| | | ||||||
| * | Update the readmev0.1.0 | Yann Herklotz | 2020-04-03 | 1 | -1/+47 | |
| | | ||||||
| * | Fix extraction on linux | Yann Herklotz | 2020-04-02 | 1 | -1/+1 | |
| | | ||||||
| * | Add gcc to build dependencies | Yann Herklotz | 2020-04-02 | 1 | -1/+3 | |
| | | ||||||
| * | Update compcert dependency | Yann Herklotz | 2020-04-02 | 2 | -0/+2 | |
| | | ||||||
| * | Update readme | Yann Herklotz | 2020-04-02 | 1 | -1/+1 | |
| | | ||||||
| * | Handle loops and conditionals correctly | Yann Herklotz | 2020-04-02 | 4 | -114/+183 | |
| | | ||||||
 |
index : vericert-kvx | |
| Unnamed repository; edit this file 'description' to name the repository. |
| aboutsummaryrefslogtreecommitdiffstats |