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* Add more legible names to variablesmichalis_merge_2dev/improved-namesYann Herklotz2021-02-121-1/+17
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* Fix state generation for if-conversionYann Herklotz2021-02-031-3/+9
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* Add predicated values and instructionsYann Herklotz2021-02-021-0/+1
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* Add correct copyright notices in filesYann Herklotz2021-01-101-0/+1
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* Fix pretty printing bug in VerilogYann Herklotz2020-11-021-2/+2
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* Fix printing of negative numbersYann Herklotz2020-10-231-1/+5
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* Add RTLBlock intermediate languageYann Herklotz2020-08-301-0/+232