| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Add RTLBlock intermediate language | Yann Herklotz | 2020-08-30 | 1 | -65/+0 |
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| * | Change name to Vericert | Yann Herklotz | 2020-07-14 | 1 | -2/+2 |
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| * | Remove admitted in mis_stepp_Vdecl | Yann Herklotz | 2020-07-05 | 1 | -3/+3 |
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| * | Finish most of Veriloggenproof | Yann Herklotz | 2020-07-05 | 1 | -18/+16 |
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| * | Fix Verilog semantics and fix order of always blocks | Yann Herklotz | 2020-06-26 | 1 | -2/+2 |
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| * | Array semantics now uses dependent Array type. | James Pollard | 2020-06-14 | 1 | -2/+3 |
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| * | Generate Verilog from HTL | Yann Herklotz | 2020-06-12 | 1 | -644/+40 |
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| * | Merge branch 'develop' into arrays-proof | James Pollard | 2020-05-30 | 1 | -20/+51 |
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| | * | Add equality check for value | Yann Herklotz | 2020-05-04 | 1 | -1/+1 |
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| | * | Add state transition conversion functions | Yann Herklotz | 2020-05-03 | 1 | -2/+14 |
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| | * | Add documentation and conform to specification | Yann Herklotz | 2020-04-29 | 1 | -24/+41 |
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| * | | Stop using tuples for register declarations | James Pollard | 2020-05-30 | 1 | -37/+39 |
| | | | | | | | | | We use a proper record type now. | ||||
| * | | Fix addressing to add support for arbitraty pointer operations | James Pollard | 2020-05-27 | 1 | -10/+19 |
| | | | | | | | | | | | | | Currently cannot guarantee alignment in some cases (single reg addressing); will need to fix this in order to prove correctness, perhaps by keeping track of alignment from LEA onwards using AbsInt? | ||||
| * | | Bug fix: stack address normalisation | James Pollard | 2020-05-26 | 1 | -1/+1 |
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| * | | (Tentatively) working stack array/memory support. | James Pollard | 2020-05-26 | 1 | -37/+50 |
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| * | | Add pattern matches and plumb through stack reg | James Pollard | 2020-05-25 | 1 | -5/+21 |
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| * | | Start work on array support | James Pollard | 2020-05-25 | 1 | -0/+1 |
| |/ | | | | Try to add a verilog register to represent the stack. | ||||
| * | Only generate clocked always blocks | Yann Herklotz | 2020-04-17 | 1 | -13/+13 |
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| * | Make proofs simpler using auto | Yann Herklotz | 2020-04-15 | 1 | -59/+45 |
| | | | | | | This makes changes to theorems easier, as the proofs will likely not have to be fixed. The runtime is also not much slower. | ||||
| * | Add proof about state wf | Yann Herklotz | 2020-04-08 | 1 | -40/+193 |
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| * | Add partial proof of well formed state | Yann Herklotz | 2020-04-06 | 1 | -24/+136 |
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| * | Handle loops and conditionals correctly | Yann Herklotz | 2020-04-02 | 1 | -100/+128 |
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| * | Complete translation from simple RTL to Verilog | Yann Herklotz | 2020-04-01 | 1 | -101/+162 |
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| * | Convert from RTL to Verilog directly | Yann Herklotz | 2020-03-31 | 1 | -18/+20 |
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| * | Add more operators and print them | Yann Herklotz | 2020-03-31 | 1 | -37/+69 |
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| * | Improve Verilog error messages | Yann Herklotz | 2020-03-31 | 1 | -1/+7 |
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| * | Rename to transf_program | Yann Herklotz | 2020-03-29 | 1 | -1/+1 |
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| * | Complete conversion from HTL to Verilog | Yann Herklotz | 2020-03-29 | 1 | -8/+91 |
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| * | Add Verilog generation from HTL | Yann Herklotz | 2020-03-29 | 1 | -0/+135 |
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index : vericert-kvx | |
| Unnamed repository; edit this file 'description' to name the repository. |
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