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path: root/src/translation/Veriloggenproof.v
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* Change name to VericertYann Herklotz2020-07-141-3/+3
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* No addmitted in VeriloggenproofYann Herklotz2020-07-051-66/+173
| | | | However, there may have been breaking changes to HTLgenproof.
* Remove admitted in mis_stepp_VdeclYann Herklotz2020-07-051-2/+6
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* Finish most of VeriloggenproofYann Herklotz2020-07-051-6/+180
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* Develop compiles againYann Herklotz2020-06-291-2/+4
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* Fix Verilog semantics and fix order of always blocksYann Herklotz2020-06-261-5/+2
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* Progress on proof of VeriloggenYann Herklotz2020-06-251-14/+19
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* Work on Veriloggen proofYann Herklotz2020-06-251-2/+50
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* Remove Verilog proofsYann Herklotz2020-06-121-19/+4
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* Add equality check for valueYann Herklotz2020-05-041-1/+1
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* Add proofs and specification of Verilog conversionYann Herklotz2020-05-031-0/+46