| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Add RTLBlock intermediate language | Yann Herklotz | 2020-08-30 | 1 | -232/+0 |
| * | More renames to get it to compile | Yann Herklotz | 2020-07-24 | 1 | -2/+4 |
| * | Change name to Vericert | Yann Herklotz | 2020-07-14 | 1 | -2/+2 |
| * | Add htl pretty printing | Yann Herklotz | 2020-06-30 | 1 | -1/+1 |
| * | Add command line flags for initial block | Yann Herklotz | 2020-06-30 | 1 | -0/+10 |
| * | Only print out main as everything is inlined | Yann Herklotz | 2020-06-22 | 1 | -8/+10 |
| * | Add print for debug always block in module | Yann Herklotz | 2020-06-22 | 1 | -5/+18 |
| * | Add more unproven instructions, Admitted equiv to spec | Yann Herklotz | 2020-06-14 | 1 | -1/+2 |
| * | Fix declaring function arguments correctly | Yann Herklotz | 2020-06-12 | 1 | -3/+3 |
| * | Fix printing of Verilog with new datatypes | Yann Herklotz | 2020-06-12 | 1 | -16/+26 |
| * | (Tentatively) working stack array/memory support. | James Pollard | 2020-05-26 | 1 | -0/+8 |
| * | Improve printing of results | Yann Herklotz | 2020-04-22 | 1 | -6/+10 |
| * | Fix printing with new Verilog AST | Yann Herklotz | 2020-04-17 | 1 | -26/+52 |
| * | Handle loops and conditionals correctly | Yann Herklotz | 2020-04-02 | 1 | -5/+45 |
| * | Update compilation | Yann Herklotz | 2020-04-01 | 1 | -8/+44 |
| * | Add more operators and print them | Yann Herklotz | 2020-03-31 | 1 | -1/+5 |
| * | Fix Verilog printing | Yann Herklotz | 2020-03-31 | 1 | -32/+34 |
| * | Rename Verilog AST files | Yann Herklotz | 2020-03-29 | 1 | -0/+74 |
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index : vericert-kvx | |
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