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| * Change AssocMap to Maps.PTreeYann Herklotz2020-05-292-50/+71
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| * Finish Assocmap proofsYann Herklotz2020-05-281-0/+59
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| * Add more proofs and remove AdmittedYann Herklotz2020-05-273-65/+94
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| * Add top level definitionYann Herklotz2020-05-272-138/+153
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| * Working on automationYann Herklotz2020-05-261-62/+48
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| * Finished proof of spec completelyYann Herklotz2020-05-262-5/+94
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| * Finished second pass and fixed bugYann Herklotz2020-05-262-18/+37
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| * Finished proving the first caseYann Herklotz2020-05-251-1/+6
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| * Continuing work on proving specificationYann Herklotz2020-05-253-22/+224
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| * Add HTLgenYann Herklotz2020-05-242-6/+341
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| * Add statemonad declarationYann Herklotz2020-05-242-0/+103
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| * Finish the proof with most assumptionsYann Herklotz2020-05-213-35/+161
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| * Add proof of translation correctnessYann Herklotz2020-05-202-17/+200
| | | | | | | | Modified-by: Yann Herklotz <git@yannherklotz.com>
| * Fix the semantics to properly evaluate the stateYann Herklotz2020-05-201-2/+4
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| * Switch position of empty ruleYann Herklotz2020-05-201-4/+4
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| * Fix definitions in Value and add lemmasYann Herklotz2020-05-201-7/+35
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| * Add theorems about mergeYann Herklotz2020-05-201-2/+12
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| * Add simulation diagramYann Herklotz2020-05-081-5/+53
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| * Add lessdef for valuesYann Herklotz2020-05-081-3/+10
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| * Add AssocMapYann Herklotz2020-05-084-47/+93
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| * Add match_states InductiveYann Herklotz2020-05-071-0/+29
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| * Remove HTLgen and create the specificationYann Herklotz2020-05-072-163/+92
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| * Redefine HTL for intermediate Verilog languageYann Herklotz2020-05-072-76/+87
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| * Use associations instead of stateYann Herklotz2020-05-072-70/+69
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| * Rename assoclist to assocsetYann Herklotz2020-05-072-28/+28
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| * Remove Admitted Maps LemmaYann Herklotz2020-05-071-6/+0
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| * Add changes to valueYann Herklotz2020-05-061-2/+9
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| * Refine test fileYann Herklotz2020-05-051-5/+2
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| * Minimised manual simulationYann Herklotz2020-05-052-45/+14
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| * Simplifications to proofYann Herklotz2020-05-053-18/+15
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| * Finish manual simulationYann Herklotz2020-05-052-5/+68
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| * Add equality check for valueYann Herklotz2020-05-047-21/+27
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| * Refine the semanticsYann Herklotz2020-05-043-56/+130
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| * Add code to debug execution of HLSsave/old-stepYann Herklotz2020-05-031-0/+73
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| * Add proofs and specification of Verilog conversionYann Herklotz2020-05-032-0/+158
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| * Add state transition conversion functionsYann Herklotz2020-05-031-2/+14
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| * Add hex notation to valuesYann Herklotz2020-05-031-0/+9
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| * Change to StateYann Herklotz2020-05-031-21/+22
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| * Add documentation and conform to specificationYann Herklotz2020-04-291-24/+41
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| * Add CompCert semantics for VerilogYann Herklotz2020-04-241-81/+152
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| * Add valueToInt functionYann Herklotz2020-04-241-0/+3
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| * Add stmnt_runp inductiveYann Herklotz2020-04-221-27/+106
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* | Stop using tuples for register declarationsJames Pollard2020-05-301-37/+39
| | | | | | | | We use a proper record type now.
* | Fix addressing to add support for arbitraty pointer operationsJames Pollard2020-05-271-10/+19
| | | | | | | | | | | | Currently cannot guarantee alignment in some cases (single reg addressing); will need to fix this in order to prove correctness, perhaps by keeping track of alignment from LEA onwards using AbsInt?
* | Bug fix: stack address normalisationJames Pollard2020-05-261-1/+1
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* | (Tentatively) working stack array/memory support.James Pollard2020-05-263-37/+62
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* | Add pattern matches and plumb through stack regJames Pollard2020-05-251-5/+21
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* | Start work on array supportJames Pollard2020-05-251-0/+1
|/ | | | Try to add a verilog register to represent the stack.
* Return the actual result of the moduleYann Herklotz2020-04-221-2/+5
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* Remove unnecessary LemmaYann Herklotz2020-04-221-8/+1
| | | | | Still cannot run these functions inside Coq itself, however, they work when they are extracted to Caml.
generated by cgit (git 2.34.1) at 2024-07-05 21:30:47 +0000