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author | Yann Herklotz <git@yannherklotz.com> | 2020-10-18 18:14:28 +0100 |
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committer | Yann Herklotz <git@yannherklotz.com> | 2020-10-18 18:14:28 +0100 |
commit | 0b1ce1ce5cde086bc67a428d69eee52c865ef1a5 (patch) | |
tree | 6c054cc675f01d98f62bd57f2d70ea62f6adc16c | |
parent | 39493b844399dba8848a004a1fd6e0906a0624f8 (diff) | |
download | vericert-0b1ce1ce5cde086bc67a428d69eee52c865ef1a5.tar.gz vericert-0b1ce1ce5cde086bc67a428d69eee52c865ef1a5.zip |
Add scheduling to driver
-rw-r--r-- | driver/VericertDriver.ml | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/driver/VericertDriver.ml b/driver/VericertDriver.ml index f500499..2b8d45f 100644 --- a/driver/VericertDriver.ml +++ b/driver/VericertDriver.ml @@ -91,14 +91,14 @@ let compile_c_file sourcename ifile ofile = close_out oc end else begin let verilog = - match Vericert.Compiler0.transf_hls csyntax with + match Vericert.Compiler0.transf_hls_temp csyntax with | Vericert.Errors.OK v -> v | Vericert.Errors.Error msg -> let loc = file_loc sourcename in fatal_error loc "%a" print_error msg in let oc = open_out ofile in - Vericert.PrintVerilog.print_program !option_debug_hls oc verilog; + Vericert.PrintRTLBlock.print_program oc verilog; close_out oc end |