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author | Yann Herklotz <git@yannherklotz.com> | 2020-11-02 19:38:43 +0000 |
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committer | Yann Herklotz <git@yannherklotz.com> | 2020-11-09 19:38:17 +0000 |
commit | 39638453bf0405b2ae58277ff3c4879b8d6d784d (patch) | |
tree | e7ac4c929c346d9e5f6fd71c3515dc380379a604 | |
parent | 82ee873033f51e856e69cea95db95e292bd0aea9 (diff) | |
download | vericert-39638453bf0405b2ae58277ff3c4879b8d6d784d.tar.gz vericert-39638453bf0405b2ae58277ff3c4879b8d6d784d.zip |
Fix pretty printing bug in Verilog
-rw-r--r-- | src/verilog/PrintVerilog.ml | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/verilog/PrintVerilog.ml b/src/verilog/PrintVerilog.ml index 353bfac..44710b8 100644 --- a/src/verilog/PrintVerilog.ml +++ b/src/verilog/PrintVerilog.ml @@ -65,7 +65,7 @@ let pprint_binop l r = | Vshru -> unsigned ">>" let unop = function - | Vneg -> " ~ " + | Vneg -> " - " | Vnot -> " ! " let register a = sprintf "reg_%d" (P.to_int a) @@ -177,7 +177,7 @@ let testbench = "module testbench; always @(posedge clk) begin if (finish == 1) begin - $display(\"finished: %d\", return_val); + $display(\"finished: %0d\", return_val); $finish; end end |