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author | Michalis Pardalos <m.pardalos@gmail.com> | 2021-01-26 16:43:58 +0200 |
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committer | Michalis Pardalos <m.pardalos@gmail.com> | 2021-01-26 16:43:58 +0200 |
commit | 53d62b4784256409be377be8ae9ad8e1ee1729cb (patch) | |
tree | 2ab63f27a4b74c733d59faa33f04c9043b9e6724 | |
parent | e86fe3f98dbc7953c0f37c020359cc91ff263e8e (diff) | |
download | vericert-53d62b4784256409be377be8ae9ad8e1ee1729cb.tar.gz vericert-53d62b4784256409be377be8ae9ad8e1ee1729cb.zip |
Separate HTL call into fork and join
-rw-r--r-- | src/translation/HTLgen.v | 28 | ||||
-rw-r--r-- | src/translation/HTLgenspec.v | 32 | ||||
-rw-r--r-- | src/translation/Veriloggen.v | 5 | ||||
-rw-r--r-- | src/verilog/HTL.v | 9 | ||||
-rw-r--r-- | src/verilog/PrintHTL.ml | 8 |
5 files changed, 62 insertions, 20 deletions
diff --git a/src/translation/HTLgen.v b/src/translation/HTLgen.v index c447b89..6a4feb5 100644 --- a/src/translation/HTLgen.v +++ b/src/translation/HTLgen.v @@ -152,6 +152,30 @@ Definition declare_reg (i : option io) (r : reg) (sz : nat) : mon unit := s.(st_controllogic)) (declare_reg_state_incr i s r sz). +Lemma create_state_state_incr: + forall s, + st_incr s (mkstate + s.(st_st) + (st_freshreg s) + (Pos.succ (st_freshstate s)) + (st_scldecls s) + (st_arrdecls s) + (st_datapath s) + (st_controllogic s)). +Proof. constructor; simpl; auto with htlh. Qed. + +Definition create_state : mon node := + fun s => let r := s.(st_freshstate) in + OK r (mkstate + s.(st_st) + (st_freshreg s) + (Pos.succ (st_freshstate s)) + (st_scldecls s) + (st_arrdecls s) + (st_datapath s) + (st_controllogic s)) + (create_state_state_incr s). + Definition add_instr (n : node) (n' : node) (st : datapath_stmnt) : mon unit := fun s => match check_empty_node_datapath s n, check_empty_node_controllogic s n with @@ -474,7 +498,9 @@ Definition transf_instr (fin rtrn stack: reg) (ni: node * instruction) : mon uni | Icall sig (inr fn) args dst n' => if Z.leb (Z.pos n') Integers.Int.max_unsigned then do _ <- declare_reg None dst 32; - add_instr n n' (HTLcall fn args dst) + do join_state <- create_state; + do _ <- add_instr n join_state (HTLfork fn args); + add_instr join_state n' (HTLjoin fn dst) else error (Errors.msg "State is larger than 2^32.") | Itailcall _ _ _ => error (Errors.msg "Tailcalls are not implemented.") | Ibuiltin _ _ _ _ => error (Errors.msg "Builtin functions not implemented.") diff --git a/src/translation/HTLgenspec.v b/src/translation/HTLgenspec.v index 44f132b..e1641b3 100644 --- a/src/translation/HTLgenspec.v +++ b/src/translation/HTLgenspec.v @@ -127,7 +127,7 @@ Inductive tr_instr (fin rtrn st stk : reg) : RTL.instruction -> datapath_stmnt - | tr_instr_Icall : forall n sig fn args dst, Z.pos n <= Int.max_unsigned -> - tr_instr fin rtrn st stk (RTL.Icall sig (inr fn) args dst n) (HTLcall fn args dst) (state_goto st n) + tr_instr fin rtrn st stk (RTL.Icall sig (inr fn) args dst n) (HTLfork fn args) (state_goto st n) | tr_instr_Icond : forall n1 n2 cond args s s' i c, Z.pos n1 <= Int.max_unsigned -> @@ -422,6 +422,13 @@ Lemma add_branch_instr_freshreg_trans : Proof. intros. unfold add_branch_instr in H. repeat (unfold_match H). inv H. auto. Qed. Hint Resolve add_branch_instr_freshreg_trans : htlspec. +Lemma create_state_freshreg_trans : + forall n s s' i, + create_state s = OK n s' i -> + s.(st_freshreg) = s'.(st_freshreg). +Proof. intros. unfold create_state in H. inv H. auto. Qed. +Hint Resolve create_state_freshreg_trans : htlspec. + Lemma add_node_skip_freshreg_trans : forall n1 n2 s r s' i, add_node_skip n1 n2 s = OK r s' i -> @@ -451,6 +458,8 @@ Proof. - unfold_match H. monadInv H. apply declare_reg_freshreg_trans in EQ. apply add_instr_freshreg_trans in EQ0. + apply create_state_freshreg_trans in EQ1. + apply add_instr_freshreg_trans in EQ3. congruence. - monadInv H. apply translate_condition_freshreg_trans in EQ. apply add_branch_instr_freshreg_trans in EQ0. congruence. @@ -551,15 +560,16 @@ Proof. eauto with htlspec. * apply in_map with (f := fst) in H2. contradiction. - + destruct o with pc1; destruct H11; simpl in *; rewrite AssocMap.gss in H9; eauto; discriminate. - + destruct o0 with pc1; destruct H11; simpl in *; rewrite AssocMap.gss in H9; eauto; discriminate. - + destruct H2. - * inversion H2. - replace (st_st s2) with (st_st s0) by congruence. - replace (st_st s1) with (st_st s0) by congruence. - econstructor. - apply Z.leb_le. assumption. - * apply in_map with (f := fst) in H2. contradiction. + + admit. (* destruct o with pc1; destruct H11; simpl in *; rewrite AssocMap.gss in H9; eauto; discriminate. *) + + admit. (* destruct o0 with pc1; destruct H11; simpl in *; rewrite AssocMap.gss in H9; eauto; discriminate. *) + + admit. + (* destruct H2. *) + (* * inversion H2. *) + (* replace (st_st s2) with (st_st s0) by congruence. *) + (* replace (st_st s1) with (st_st s0) by congruence. *) + (* econstructor. *) + (* apply Z.leb_le. assumption. *) + (* * apply in_map with (f := fst) in H2. contradiction. *) + destruct o with pc1; destruct H11; simpl in *; rewrite AssocMap.gss in H9; eauto; congruence. + destruct o0 with pc1; destruct H11; simpl in *; rewrite AssocMap.gss in H9; eauto; congruence. @@ -596,7 +606,7 @@ Proof. destruct H2. inversion H2. subst. contradiction. intros. specialize H1 with pc0 instr0. destruct H1. tauto. trivial. destruct H2. inv H2. contradiction. assumption. assumption. -Qed. +Admitted. Hint Resolve iter_expand_instr_spec : htlspec. Lemma create_arr_inv : forall w x y z a b c d, diff --git a/src/translation/Veriloggen.v b/src/translation/Veriloggen.v index a27a6a5..b3557fd 100644 --- a/src/translation/Veriloggen.v +++ b/src/translation/Veriloggen.v @@ -52,7 +52,8 @@ Definition transl_datapath_fun (a : Verilog.node * HTL.datapath_stmnt) := let (n, s) := a in (Verilog.Vlit (posToValue n), match s with - | HTL.HTLcall m args dst => Verilog.Vskip (* inline_call m args *) + | HTL.HTLfork m args => Verilog.Vskip (* inline_call m args *) + | HTL.HTLjoin m dst => Verilog.Vskip (* inline_call m args *) | HTL.HTLVstmnt s => s end). @@ -222,7 +223,7 @@ Section TRANSLATE. List.nodup Pos.eq_dec (flat_map (fun (a : (positive * HTL.datapath_stmnt)) => let (n, stmt) := a in match stmt with - | HTL.HTLcall fn _ _ => fn::nil + | HTL.HTLfork fn _ => fn::nil | _ => nil end) stmnts). diff --git a/src/verilog/HTL.v b/src/verilog/HTL.v index ca4270b..d309033 100644 --- a/src/verilog/HTL.v +++ b/src/verilog/HTL.v @@ -35,7 +35,8 @@ Definition node := positive. Definition ident := positive. Inductive datapath_stmnt := -| HTLcall : ident -> list reg -> reg -> datapath_stmnt +| HTLfork : ident -> list reg -> datapath_stmnt +| HTLjoin : ident -> reg -> datapath_stmnt | HTLVstmnt : Verilog.stmnt -> datapath_stmnt. Definition datapath := PTree.t datapath_stmnt. @@ -110,8 +111,10 @@ Inductive datapath_stmnt_runp: Verilog.fext -> Verilog.reg_associations -> Verilog.arr_associations -> datapath_stmnt -> Verilog.reg_associations -> Verilog.arr_associations -> Prop := (* TODO give it an actual semantics *) -| stmnt_runp_HTLcall : forall f ar al i args dst, - datapath_stmnt_runp f ar al (HTLcall i args dst) ar al +| stmnt_runp_HTLfork : forall f ar al i args, + datapath_stmnt_runp f ar al (HTLfork i args) ar al +| stmnt_runp_HTLcall : forall f ar al i dst, + datapath_stmnt_runp f ar al (HTLjoin i dst) ar al | stmnt_runp_HTLVstmnt : forall asr0 asa0 asr1 asa1 f stmnt, Verilog.stmnt_runp f asr0 asa0 stmnt asr1 asa1 -> datapath_stmnt_runp f asr0 asa0 (HTLVstmnt stmnt) asr1 asa1. diff --git a/src/verilog/PrintHTL.ml b/src/verilog/PrintHTL.ml index fd6cf49..430a4b4 100644 --- a/src/verilog/PrintHTL.ml +++ b/src/verilog/PrintHTL.ml @@ -46,9 +46,11 @@ let print_instruction pp (pc, i) = let pprint_datapath_stmnt i = function | HTLVstmnt s -> pprint_stmnt i s - | HTLcall (name, args, dst) -> concat [ - register dst; " = "; - extern_atom name; "("; concat (intersperse ", " (List.map register args)); ");\n" + | HTLfork (name, args) -> concat [ + "fork "; extern_atom name; "("; concat (intersperse ", " (List.map register args)); ");\n" + ] + | HTLjoin (name, dst) -> concat [ + register dst; " <= join "; extern_atom name; ";\n" ] let print_datapath_instruction pp (pc, i) = |