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author | Yann Herklotz <git@yannherklotz.com> | 2021-07-07 22:21:20 +0200 |
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committer | Yann Herklotz <git@yannherklotz.com> | 2021-07-07 22:21:20 +0200 |
commit | 8273bfff6ab40cd7c0e0f316551e17e509c46a47 (patch) | |
tree | 5e26d385cc6229ed21b150cfa0b1d1ebfc39d257 | |
parent | da56228e5938fd835910e7aaf345c1ff684234e8 (diff) | |
download | vericert-8273bfff6ab40cd7c0e0f316551e17e509c46a47.tar.gz vericert-8273bfff6ab40cd7c0e0f316551e17e509c46a47.zip |
Add changelog which mentions the RAM support
-rw-r--r-- | CHANGELOG.org | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/CHANGELOG.org b/CHANGELOG.org index 621683c..108dc30 100644 --- a/CHANGELOG.org +++ b/CHANGELOG.org @@ -10,6 +10,7 @@ RTL. - Add *RTLPar*, which can execute groups of instructions in parallel. - Add scheduling pass to go from RTLBlock to RTLPar. +- Proper RAM inference support. ** v1.1.0 - 2020-12-17 |