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| author | Yann Herklotz <git@yannherklotz.com> | 2021-08-12 02:03:14 +0200 |
|---|---|---|
| committer | Yann Herklotz <git@yannherklotz.com> | 2021-08-12 02:03:14 +0200 |
| commit | d023058aceaa5309ee00e99744fe0c9f5df15ced (patch) | |
| tree | 981521d11b27a6eec9b9330c12d28a1c03ecc6f9 | |
| parent | 0c021173b3efb1310370de4b2a6f5444c745022f (diff) | |
| download | vericert-d023058aceaa5309ee00e99744fe0c9f5df15ced.tar.gz vericert-d023058aceaa5309ee00e99744fe0c9f5df15ced.zip | |
Fix pretty printing issue in Verilog
| -rw-r--r-- | src/hls/PrintVerilog.ml | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/hls/PrintVerilog.ml b/src/hls/PrintVerilog.ml index a2700a1..a5fa554 100644 --- a/src/hls/PrintVerilog.ml +++ b/src/hls/PrintVerilog.ml @@ -75,7 +75,7 @@ let pprint_binop l r = let unop = function | Vneg -> " - " - | Vnot -> " ! " + | Vnot -> " ~ " let register a = match PMap.find_opt a !name_map with |