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| author | Yann Herklotz <git@yannherklotz.com> | 2023-10-20 10:48:09 +0100 |
|---|---|---|
| committer | Yann Herklotz <git@yannherklotz.com> | 2023-10-20 10:48:09 +0100 |
| commit | 26db7d1fe8c93e88ccecc33254d75e4b90844545 (patch) | |
| tree | d6821bcc3b003d526870b973de2a116be0111400 | |
| parent | 684a250e27c7bbbad6b8a60e789dc7d90a9ce16c (diff) | |
| download | vericert-26db7d1fe8c93e88ccecc33254d75e4b90844545.tar.gz vericert-26db7d1fe8c93e88ccecc33254d75e4b90844545.zip | |
Fix compilation without FunctionUnits
| -rw-r--r-- | src/hls/PrintVerilog.ml | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/hls/PrintVerilog.ml b/src/hls/PrintVerilog.ml index 2e0f0e1..a096bd1 100644 --- a/src/hls/PrintVerilog.ml +++ b/src/hls/PrintVerilog.ml @@ -28,7 +28,7 @@ open Clflags open Printf open VericertClflags -open FunctionalUnits +(* open FunctionalUnits *) module PMap = Map.Make (struct type t = P.t |