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| author | Yann Herklotz <git@yannherklotz.com> | 2021-10-12 13:38:38 +0100 |
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| committer | Yann Herklotz <git@yannherklotz.com> | 2021-10-12 13:38:38 +0100 |
| commit | b4e70337d1c0d1130ec9c98e7fe6e52dbfee46a5 (patch) | |
| tree | 2446ae118e6e1cfd750e9926925bcce1e69f9255 /CHANGELOG.org | |
| parent | 06b24257359305114b868b5b78971cc4c6e30db1 (diff) | |
| parent | 11c5cc2ce59fe68959fe424fc04d4e947432abcb (diff) | |
| download | vericert-b4e70337d1c0d1130ec9c98e7fe6e52dbfee46a5.tar.gz vericert-b4e70337d1c0d1130ec9c98e7fe6e52dbfee46a5.zip | |
Merge branch 'dev/scheduling' of git.ymhg.org:vericert into dev/scheduling
Diffstat (limited to 'CHANGELOG.org')
| -rw-r--r-- | CHANGELOG.org | 10 |
1 files changed, 7 insertions, 3 deletions
diff --git a/CHANGELOG.org b/CHANGELOG.org index 66f754d..88c0953 100644 --- a/CHANGELOG.org +++ b/CHANGELOG.org @@ -7,10 +7,14 @@ ** New Features -- Add *RTLBlock*, a basic block intermediate language that is based on CompCert's +- Add ~RTLBlock~, a basic block intermediate language that is based on CompCert's RTL. -- Add *RTLPar*, which can execute groups of instructions in parallel. -- Add scheduling pass to go from RTLBlock to RTLPar. +- Add ~RTLPar~, which can execute groups of instructions in parallel. +- Add SDC hyper-block scheduling pass to go from RTLBlock to RTLPar using. +- Add operation chaining support to scheduler. +- Add ~Abstr~ intermediate language for equivalence checking of schedule. +- Add built-in verified SAT solver used for equivalence checking of + hyper-blocks. * 2021-10-01 - v1.2.2 |