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author | Yann Herklotz <git@yannherklotz.com> | 2021-07-07 22:23:53 +0200 |
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committer | Yann Herklotz <git@yannherklotz.com> | 2021-07-07 22:23:53 +0200 |
commit | c4d44af5f3135aba4d4878f8f41c80d1f0b9e9a2 (patch) | |
tree | ce91ee822c2dc8683c0a1369f4833415b1c64968 /CHANGELOG.org | |
parent | 8273bfff6ab40cd7c0e0f316551e17e509c46a47 (diff) | |
download | vericert-c4d44af5f3135aba4d4878f8f41c80d1f0b9e9a2.tar.gz vericert-c4d44af5f3135aba4d4878f8f41c80d1f0b9e9a2.zip |
New release information to the changelog
Diffstat (limited to 'CHANGELOG.org')
-rw-r--r-- | CHANGELOG.org | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/CHANGELOG.org b/CHANGELOG.org index 108dc30..52db994 100644 --- a/CHANGELOG.org +++ b/CHANGELOG.org @@ -10,6 +10,9 @@ RTL. - Add *RTLPar*, which can execute groups of instructions in parallel. - Add scheduling pass to go from RTLBlock to RTLPar. + +** v1.2.0 - 2021-04-07 + - Proper RAM inference support. ** v1.1.0 - 2020-12-17 |