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author | Yann Herklotz <git@yannherklotz.com> | 2020-08-10 18:56:55 +0200 |
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committer | Yann Herklotz <git@yannherklotz.com> | 2020-08-10 18:56:55 +0200 |
commit | f07e5886be419f776caaf3dc20f7017fe94512b5 (patch) | |
tree | fa130734012c3ab1af2233e13f8b3572be3e48c0 /README.md | |
parent | c9f61e391cd597844af93dd2014d9668798e712e (diff) | |
download | vericert-f07e5886be419f776caaf3dc20f7017fe94512b5.tar.gz vericert-f07e5886be419f776caaf3dc20f7017fe94512b5.zip |
Add badge for admitted proofs
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-rw-r--r-- | README.md | 1 |
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@@ -1,6 +1,7 @@ # Vericert ![CI](https://github.com/ymherklotz/vericert/workflows/CI/badge.svg) +![Admitted](https://ymherklotz.github.io/vericert/assets/admitted.svg) A formally verified high-level synthesis (HLS) tool written in Coq, building on top of [CompCert](https://github.com/AbsInt/CompCert). This ensures the correctness of the C to Verilog translation according to our Verilog semantics and CompCert's C semantics, removing the need to check the resulting hardware for behavioural correctness. |