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authorYann Herklotz <git@yannherklotz.com>2020-08-10 19:04:21 +0200
committerYann Herklotz <git@yannherklotz.com>2020-08-10 19:04:21 +0200
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# Vericert
![CI](https://github.com/ymherklotz/vericert/workflows/CI/badge.svg)
-![Admitted](https://ymherklotz.github.io/vericert/assets/admitted.svg)
+![Admitted](https://raw.githubusercontent.com/ymherklotz/vericert/gh-pages/assets/admitted.svg)
A formally verified high-level synthesis (HLS) tool written in Coq, building on top of [CompCert](https://github.com/AbsInt/CompCert). This ensures the correctness of the C to Verilog translation according to our Verilog semantics and CompCert's C semantics, removing the need to check the resulting hardware for behavioural correctness.