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author | Yann Herklotz <git@yannherklotz.com> | 2020-08-10 19:04:21 +0200 |
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committer | Yann Herklotz <git@yannherklotz.com> | 2020-08-10 19:04:21 +0200 |
commit | c64d5992e5c14d2dad7b528a37001ea7690d649e (patch) | |
tree | 1891466bf91a648040543ad7811b7dc578df5c6a /README.md | |
parent | 8dfd752666c2ab1d87523e9e1caf25b0413d65a7 (diff) | |
download | vericert-c64d5992e5c14d2dad7b528a37001ea7690d649e.tar.gz vericert-c64d5992e5c14d2dad7b528a37001ea7690d649e.zip |
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@@ -1,7 +1,7 @@ # Vericert ![CI](https://github.com/ymherklotz/vericert/workflows/CI/badge.svg) -![Admitted](https://ymherklotz.github.io/vericert/assets/admitted.svg) +![Admitted](https://raw.githubusercontent.com/ymherklotz/vericert/gh-pages/assets/admitted.svg) A formally verified high-level synthesis (HLS) tool written in Coq, building on top of [CompCert](https://github.com/AbsInt/CompCert). This ensures the correctness of the C to Verilog translation according to our Verilog semantics and CompCert's C semantics, removing the need to check the resulting hardware for behavioural correctness. |