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authorYann Herklotz <git@yannherklotz.com>2022-06-24 18:28:53 +0100
committerYann Herklotz <git@yannherklotz.com>2022-06-24 18:28:53 +0100
commit56f1dd7a658dd21bb267dc41fc0301adbd620a6d (patch)
tree12f55df14f2e73a7b14f461cee837e79b15cb502 /doc/index.rst
parent0a7f2f6f6e0f68a9fa89a27dc677b40f8dfb6e86 (diff)
downloadvericert-56f1dd7a658dd21bb267dc41fc0301adbd620a6d.tar.gz
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Update build files for documentation
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diff --git a/doc/index.rst b/doc/index.rst
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@@ -33,9 +33,11 @@ have all been proven correct, providing a verified translation from C to Verilog
:caption: Sources
src/Compiler
- src/hls/RTLBlockInstr
- src/hls/RTLBlockgen
- src/hls/RTLBlockgenproof
+ src/hls/Gible.v
+ src/hls/GibleSeq.v
+ src/hls/GiblePar.v
+ src/hls/GibleSeqgen.v
+ src/hls/GibleSeqgenproof.v
Publications
------------