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author | Yann Herklotz <git@yannherklotz.com> | 2020-02-14 21:02:44 +0000 |
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committer | Yann Herklotz <git@yannherklotz.com> | 2020-02-14 21:02:44 +0000 |
commit | ff40ff40ee967f6fd9206ef8c86426b0ea33cbde (patch) | |
tree | 81bfa37c75c73feb0131a2856c20ec81357222a2 /example/main.v | |
parent | c1f2c2e386c2597fdc61509ab2376f61f120c119 (diff) | |
download | vericert-ff40ff40ee967f6fd9206ef8c86426b0ea33cbde.tar.gz vericert-ff40ff40ee967f6fd9206ef8c86426b0ea33cbde.zip |
Update driver
Diffstat (limited to 'example/main.v')
-rw-r--r-- | example/main.v | 79 |
1 files changed, 79 insertions, 0 deletions
diff --git a/example/main.v b/example/main.v new file mode 100644 index 0000000..63130fe --- /dev/null +++ b/example/main.v @@ -0,0 +1,79 @@ +// -*- mode: verilog -*- + +module main(input start, reset, clk, + output finished, output [31:0] return_val); + + reg [31:0] x; + reg [31:0] y; + reg [31:0] z; + reg [2:0] state; + + reg [31:0] return_val_w; + reg finished_w; + + localparam [2:0] START_STATE = 0; + localparam [2:0] MAIN_STATE_0 = 1; + localparam [2:0] MAIN_STATE_1 = 2; + localparam [2:0] MAIN_STATE_2 = 3; + localparam [2:0] MAIN_STATE_3 = 4; + localparam [2:0] MAIN_STATE_4 = 5; + localparam [2:0] FINISHED_STATE = 6; + + assign return_val = return_val_w; + assign finished = finished_w; + + always @(posedge clk) + if (reset) begin + state <= START_STATE; + return_val_w <= 0; + finished_w <= 0; + end + else + case (state) + START_STATE: x <= 0; + MAIN_STATE_0: y <= 0; + MAIN_STATE_1: z <= 0; + MAIN_STATE_2: y <= 2; + MAIN_STATE_3: z <= 3; + MAIN_STATE_4: x <= y * z; + FINISHED_STATE: begin + return_val_w <= x; + finished_w <= 1; + end + default: state <= START_STATE; + endcase + + always @(posedge clk) + if (state != FINISHED_STATE) + state <= state + 1; + +endmodule + +module testbench; + reg start, reset, clk; + wire finished; + wire [31:0] return_val; + + main main(start, reset, clk, finished, return_val); + + initial begin + $dumpvars; + start = 0; + reset = 1; + clk = 0; + + @(posedge clk) begin + reset = 0; + start = 1; + end + @(posedge clk) start = 0; + + #100; + + $display("Result: %d", return_val); + $finish; + end + + always #5 clk = ~clk; + +endmodule |