Fix backend hardware generation and scheduling

4 files changed, 11 insertions, 11 deletions

diff --git a/scripts/synth-ssh.sh b/scripts/synth-ssh.sh
index a6ce349..ca255e1 100755
--- a/scripts/synth-ssh.sh
+++ b/scripts/synth-ssh.sh
@@ -1,4 +1,4 @@
-#!/usr/bin/bash
+#!/usr/bin/env bash
 
 # Assumes that the Verilog is passed on the command line, that the tcl file is in synth.tcl and
 # returns encode_report.xml.
@@ -10,19 +10,19 @@ bench=$2
 output=$3
 machine=ee-beholder${num}.ee.ic.ac.uk
 user=ymh15
-files="$scriptsdir/synth.tcl $output/$bench.v"
+files="$scriptsdir/synth.tcl $output/$bench.sv"
 log="$output/${bench}_synth.log"
 
 date >$log
 
-temp=$(ssh $user@$machine "mktemp -d" 2>>$log)
+temp=$(ssh $user@$machine "mktemp -d")
 
 >&2 echo "synthesising $bench $temp"
 rsync $files $user@$machine:$temp/ >>$log 2>&1
 ssh $user@$machine \
-    "bash -lc 'cd $temp && cp $(basename $bench).v main.v && vivado -mode batch -source synth.tcl'" \
+    "bash -lc 'cd $temp && cp $(basename $bench).sv main.sv && vivado -mode batch -source synth.tcl'" \
     >>$log 2>&1
 rsync $user@$machine:$temp/encode_report.xml $output/${bench}_report.xml >>$log 2>&1
-ssh $user@$machine "rm -rf '$temp'" >>$log 2>&1
-rm -f main.v >>$log 2>&1
+# ssh $user@$machine "rm -rf '$temp'" >>$log 2>&1
+rm -f main.sv >>$log 2>&1
 >&2 echo "done $bench"
diff --git a/scripts/synth.sh b/scripts/synth.sh
index b1c2696..d459dd3 100755
--- a/scripts/synth.sh
+++ b/scripts/synth.sh
@@ -1,4 +1,4 @@
-#!/usr/bin/bash
+#!/usr/bin/env bash
 
 set -x
 
@@ -24,9 +24,9 @@ fi
 
 echo "copying directory structure from $source to $output"
 mkdir -p $output
-rsync -am --include '*/' --include '*.v' --exclude '*' $source/ $output/
+rsync -am --include '*/' --include '*.sv' --exclude '*' $source/ $output/
 
 echo "executing $parallel runs in parallel"
-cat $scriptsdir/../benchmarks/polybench-syn/benchmark-list-master | \
+cat ./benchmark-list-master | \
     xargs --max-procs=$parallel --replace=% \
     $scriptsdir/synth-ssh.sh 0 % $output
diff --git a/scripts/synth.tcl b/scripts/synth.tcl
index a2fb722..f5a2388 100644
--- a/scripts/synth.tcl
+++ b/scripts/synth.tcl
@@ -76,7 +76,7 @@ proc dump_statistics {  } {
 }; #END PROC
 set outputDir .
 create_project -in_memory -part xc7z020clg484-1 -force
-read_verilog -sv main.v
+read_verilog -sv main.sv
 synth_design -mode out_of_context -no_iobuf -top main -part xc7z020clg484-1
 write_checkpoint -force $outputDir/post_synth.dcp
 report_timing_summary -file $outputDir/post_synth_timing_summary.rpt
diff --git a/scripts/synthesis-results.scm b/scripts/synthesis-results.scm
index b1a7349..3760cfb 100755
--- a/scripts/synthesis-results.scm
+++ b/scripts/synthesis-results.scm
@@ -1,4 +1,4 @@
-#! /usr/bin/chicken-csi -ss
+#! /usr/local/bin/csi -ss
 ;; -*- mode: scheme -*-
 ;;
 ;; Copyright (C) 2022 Yann Herklotz <yann@yannherklotz.com>