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| author | Yann Herklotz <git@yannherklotz.com> | 2021-03-02 10:27:43 +0000 |
|---|---|---|
| committer | Yann Herklotz <git@yannherklotz.com> | 2021-03-02 10:27:43 +0000 |
| commit | 5b121800db192b3d31cb6a245529f876079f442e (patch) | |
| tree | 1a9e9f80aa73de332b505851a8a35eba71ee0ec7 /src/Compiler.v | |
| parent | 05347ca5126f335b0479b71a4576b141e082fab5 (diff) | |
| download | vericert-5b121800db192b3d31cb6a245529f876079f442e.tar.gz vericert-5b121800db192b3d31cb6a245529f876079f442e.zip | |
Add option to turn on/off ram inferrence
Diffstat (limited to 'src/Compiler.v')
| -rw-r--r-- | src/Compiler.v | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/src/Compiler.v b/src/Compiler.v index d99ce56..4e4665b 100644 --- a/src/Compiler.v +++ b/src/Compiler.v @@ -69,6 +69,7 @@ Require vericert.hls.HTLPargen. Require vericert.hls.Pipeline. Require vericert.hls.IfConversion. Require vericert.HLSOpts. +Require vericert.hls.Memorygen. Require Import vericert.hls.HTLgenproof. @@ -191,6 +192,7 @@ Definition transf_backend (r : RTL.program) : res Verilog.program := @@ print (print_RTL 7) @@@ HTLgen.transl_program @@ print print_HTL + @@ total_if HLSOpts.optim_ram Memorygen.transf_program @@ Veriloggen.transl_program. (*| @@ -321,8 +323,8 @@ Proof. exists p13; split. apply Unusedglobproof.transf_program_match; auto. exists p14; split. apply HTLgenproof.transf_program_match; auto. exists p15; split. apply Veriloggenproof.transf_program_match; auto. - inv T. reflexivity. -Qed. + inv T. Admitted. (*reflexivity. +Qed.*) Theorem cstrategy_semantic_preservation: forall p tp, |