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| author | Yann Herklotz <git@yannherklotz.com> | 2020-04-01 19:24:29 +0100 |
|---|---|---|
| committer | Yann Herklotz <git@yannherklotz.com> | 2020-04-01 19:24:29 +0100 |
| commit | 981b6238573548b696d0a4a50eb7605387245c0b (patch) | |
| tree | 9c3ca289869da701b3862f925f9640f875fd202b /src/Compiler.v | |
| parent | 9161696a5056939086d1f372b9ae1f274094dad7 (diff) | |
| download | vericert-981b6238573548b696d0a4a50eb7605387245c0b.tar.gz vericert-981b6238573548b696d0a4a50eb7605387245c0b.zip | |
Update compilation
Diffstat (limited to 'src/Compiler.v')
| -rw-r--r-- | src/Compiler.v | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/Compiler.v b/src/Compiler.v index 7a88839..5b4ef0a 100644 --- a/src/Compiler.v +++ b/src/Compiler.v @@ -74,7 +74,7 @@ Proof. intros. destruct x; simpl. rewrite print_identity. auto. auto. Qed. -Definition transf_backend (r : RTL.program) : res Verilog.verilog := +Definition transf_backend (r : RTL.program) : res Verilog.module := OK r @@@ Veriloggen.transf_program. @@ -88,7 +88,7 @@ Definition transf_frontend (p: Csyntax.program) : res RTL.program := @@@ RTLgen.transl_program @@ print (print_RTL 0). -Definition transf_hls (p : Csyntax.program) : res Verilog.verilog := +Definition transf_hls (p : Csyntax.program) : res Verilog.module := OK p @@@ transf_frontend @@@ transf_backend. |