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| author | Yann Herklotz <git@yannherklotz.com> | 2020-04-17 14:55:57 +0100 |
|---|---|---|
| committer | Yann Herklotz <git@yannherklotz.com> | 2020-04-17 14:55:57 +0100 |
| commit | ae30c51b001b43e292c1e2b48799bf197d7b89ec (patch) | |
| tree | 2178b075fb0fee981eda853b631ac191a89a7280 /src/Compiler.v | |
| parent | 5ea04d4bbec608cfe54f8722774ed581c9834c2a (diff) | |
| download | vericert-ae30c51b001b43e292c1e2b48799bf197d7b89ec.tar.gz vericert-ae30c51b001b43e292c1e2b48799bf197d7b89ec.zip | |
Extract simulator
Diffstat (limited to 'src/Compiler.v')
| -rw-r--r-- | src/Compiler.v | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/Compiler.v b/src/Compiler.v index 5b4ef0a..697732d 100644 --- a/src/Compiler.v +++ b/src/Compiler.v @@ -1,4 +1,4 @@ -(* +(* -*- mode: coq -*- * CoqUp: Verified high-level synthesis. * Copyright (C) 2019-2020 Yann Herklotz <yann@yannherklotz.com> * @@ -74,7 +74,7 @@ Proof. intros. destruct x; simpl. rewrite print_identity. auto. auto. Qed. -Definition transf_backend (r : RTL.program) : res Verilog.module := +Definition transf_backend (r : RTL.program) : res Verilog.module := OK r @@@ Veriloggen.transf_program. |