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| author | Yann Herklotz <git@yannherklotz.com> | 2021-02-02 12:55:37 +0000 |
|---|---|---|
| committer | Yann Herklotz <git@yannherklotz.com> | 2021-02-02 12:55:37 +0000 |
| commit | cf9323858362f2c7d4f1ecd99c7bf93d30cf5ea3 (patch) | |
| tree | 4809a93cbeedeed48d062efa1c434da458c6d7e3 /src/Compiler.v | |
| parent | 3b77ad9c0f3c52ba1cc02f954ee5bc2b63f51366 (diff) | |
| download | vericert-cf9323858362f2c7d4f1ecd99c7bf93d30cf5ea3.tar.gz vericert-cf9323858362f2c7d4f1ecd99c7bf93d30cf5ea3.zip | |
Add Vrange and predicates
Diffstat (limited to 'src/Compiler.v')
| -rw-r--r-- | src/Compiler.v | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/src/Compiler.v b/src/Compiler.v index 0578f57..2406dad 100644 --- a/src/Compiler.v +++ b/src/Compiler.v @@ -232,8 +232,6 @@ Definition transf_hls_temp (p : Csyntax.program) : res Verilog.program := @@ print (print_RTL 6) @@@ time "Unused globals" Unusedglob.transform_program @@ print (print_RTL 7) - @@ Pipeline.transf_program - @@ print (print_RTL 8) @@@ RTLBlockgen.transl_program @@ print print_RTLBlock @@@ RTLPargen.transl_program |