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| author | Yann Herklotz <git@yannherklotz.com> | 2021-10-18 17:05:46 +0100 |
|---|---|---|
| committer | Yann Herklotz <git@yannherklotz.com> | 2021-10-18 17:05:46 +0100 |
| commit | fbfa988072ce2eba808b9a6631af5f8e86cd9df0 (patch) | |
| tree | 5146e558d5c9c6e9a399225eed0784b8dc12558f /src/extraction | |
| parent | 603768a49eac2005729dd03e723ff6c5a6b292f7 (diff) | |
| parent | fe06668f0de56635efe55310d7a64289a37c1d90 (diff) | |
| download | vericert-dev/michalis.tar.gz vericert-dev/michalis.zip | |
Merge branch 'master' into dev/michalisdev/michalis
Diffstat (limited to 'src/extraction')
| -rw-r--r-- | src/extraction/Extraction.v | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/src/extraction/Extraction.v b/src/extraction/Extraction.v index 6abe4e0..97f0d2a 100644 --- a/src/extraction/Extraction.v +++ b/src/extraction/Extraction.v @@ -144,6 +144,7 @@ Extract Constant driver.Compiler.print_RTL => "PrintRTL.print_if". Extract Constant Compiler.print_RTL => "PrintRTL.print_if". Extract Constant Compiler.print_RTLBlock => "PrintRTLBlock.print_if". Extract Constant Compiler.print_HTL => "PrintHTL.print_if". +Extract Constant Compiler.print_RTLPar => "PrintRTLPar.print_if". Extract Constant Compiler.print_LTL => "PrintLTL.print_if". Extract Constant Compiler.print_Mach => "PrintMach.print_if". Extract Constant Compiler.print => "fun (f: 'a -> unit) (x: 'a) -> f x; x". @@ -179,7 +180,7 @@ Extract Inlined Constant Bracket.inbetween_loc => "fun _ -> assert false". Extract Constant Pipeline.pipeline => "SoftwarePipelining.pipeline". Extract Constant RTLBlockgen.partition => "Partition.partition". -(*Extract Constant RTLPargen.schedule => "Schedule.schedule_fn".*) +Extract Constant RTLPargen.schedule => "Schedule.schedule_fn". (* Needed in Coq 8.4 to avoid problems with Function definitions. *) Set Extraction AccessOpaque. @@ -187,11 +188,11 @@ Set Extraction AccessOpaque. Cd "src/extraction". Separate Extraction Verilog.module vericert.Compiler.transf_hls -(* vericert.Compiler.transf_hls_temp*) -(* RTLBlockgen.transl_program RTLBlockInstr.successors_instr*) + vericert.Compiler.transf_hls_temp + RTLBlockgen.transl_program RTLBlockInstr.successors_instr HTLgen.tbl_to_case_expr Pipeline.pipeline -(* RTLBlockInstr.sat_pred_temp*) + RTLBlockInstr.sat_pred_simple Verilog.stmnt_to_list Compiler.transf_c_program Compiler.transf_cminor_program |