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| author | Yann Herklotz <git@yannherklotz.com> | 2021-07-11 15:59:21 +0200 |
|---|---|---|
| committer | Yann Herklotz <git@yannherklotz.com> | 2021-07-11 15:59:21 +0200 |
| commit | 178a7c4781c96857fe0a33c777da83e769516152 (patch) | |
| tree | cf4b5248a144289c84161a6fd73de37523c9d373 /src/extraction | |
| parent | 3dfc30619a4f3ecf0f262481a0891259c2b37ed1 (diff) | |
| download | vericert-178a7c4781c96857fe0a33c777da83e769516152.tar.gz vericert-178a7c4781c96857fe0a33c777da83e769516152.zip | |
Remove unnecessary files and proofs
Diffstat (limited to 'src/extraction')
| -rw-r--r-- | src/extraction/Extraction.v | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/extraction/Extraction.v b/src/extraction/Extraction.v index 00a1f00..6abe4e0 100644 --- a/src/extraction/Extraction.v +++ b/src/extraction/Extraction.v @@ -179,7 +179,7 @@ Extract Inlined Constant Bracket.inbetween_loc => "fun _ -> assert false". Extract Constant Pipeline.pipeline => "SoftwarePipelining.pipeline". Extract Constant RTLBlockgen.partition => "Partition.partition". -Extract Constant RTLPargen.schedule => "Schedule.schedule_fn". +(*Extract Constant RTLPargen.schedule => "Schedule.schedule_fn".*) (* Needed in Coq 8.4 to avoid problems with Function definitions. *) Set Extraction AccessOpaque. @@ -187,11 +187,11 @@ Set Extraction AccessOpaque. Cd "src/extraction". Separate Extraction Verilog.module vericert.Compiler.transf_hls - vericert.Compiler.transf_hls_temp - RTLBlockgen.transl_program RTLBlockInstr.successors_instr +(* vericert.Compiler.transf_hls_temp*) +(* RTLBlockgen.transl_program RTLBlockInstr.successors_instr*) HTLgen.tbl_to_case_expr Pipeline.pipeline - RTLBlockInstr.sat_pred_temp +(* RTLBlockInstr.sat_pred_temp*) Verilog.stmnt_to_list Compiler.transf_c_program Compiler.transf_cminor_program |