diff options
| author | Yann Herklotz <git@yannherklotz.com> | 2021-03-02 10:27:33 +0000 |
|---|---|---|
| committer | Yann Herklotz <git@yannherklotz.com> | 2021-03-02 10:27:33 +0000 |
| commit | 05347ca5126f335b0479b71a4576b141e082fab5 (patch) | |
| tree | b4dc63f00ca3b8158ad11ea77fafd4cec382c95f /src/hls/HTL.v | |
| parent | 8ddf6a9ff669fbc28cb3247c6ce40cb8fa4cc3fc (diff) | |
| download | vericert-05347ca5126f335b0479b71a4576b141e082fab5.tar.gz vericert-05347ca5126f335b0479b71a4576b141e082fab5.zip | |
Add RAM to HTL
Diffstat (limited to 'src/hls/HTL.v')
| -rw-r--r-- | src/hls/HTL.v | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/hls/HTL.v b/src/hls/HTL.v index c8a0041..1949785 100644 --- a/src/hls/HTL.v +++ b/src/hls/HTL.v @@ -67,6 +67,7 @@ Record module: Type := mod_clk : reg; mod_scldecls : AssocMap.t (option Verilog.io * Verilog.scl_decl); mod_arrdecls : AssocMap.t (option Verilog.io * Verilog.arr_decl); + mod_ram : option (reg * reg * reg * reg); mod_wf : (map_well_formed mod_controllogic /\ map_well_formed mod_datapath); }. |