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author | Michalis Pardalos <m.pardalos@gmail.com> | 2021-09-01 14:06:51 +0100 |
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committer | Michalis Pardalos <m.pardalos@gmail.com> | 2021-09-01 14:06:51 +0100 |
commit | e4a173f4ebd46b5e3f45ee4f65a93790d68544ab (patch) | |
tree | 10494f0357c404604eb8756f6deb0f15d53d576a /src/hls/HTL.v | |
parent | adabec157b807bf6695bdcef64233c76f43c37bb (diff) | |
download | vericert-e4a173f4ebd46b5e3f45ee4f65a93790d68544ab.tar.gz vericert-e4a173f4ebd46b5e3f45ee4f65a93790d68544ab.zip |
Use sumbool instead of option for decide_ram_wf
Diffstat (limited to 'src/hls/HTL.v')
-rw-r--r-- | src/hls/HTL.v | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/src/hls/HTL.v b/src/hls/HTL.v index 3116af3..303dc70 100644 --- a/src/hls/HTL.v +++ b/src/hls/HTL.v @@ -448,16 +448,16 @@ Definition decide_order a b c d e f g : {module_ordering a b c d e f g} + {True} end; unfold module_ordering; auto. Defined. -Definition option_ram_wf (clk : reg) (mr : option HTL.ram) : - option (forall r' : ram, mr = Some r' -> (clk < ram_addr r')%positive). +Definition decide_ram_wf (clk : reg) (mr : option HTL.ram) : + {forall r' : ram, mr = Some r' -> (clk < ram_addr r')%positive} + {True}. refine ( match mr with | Some r => match (plt clk (ram_addr r)) with - | left LE => Some _ - | _ => None + | left LE => left _ + | _ => right I end - | None => None + | None => left _ end). - crush. + all: crush. Defined. |