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| author | Yann Herklotz <git@yannherklotz.com> | 2021-10-14 12:20:03 +0100 |
|---|---|---|
| committer | Yann Herklotz <git@yannherklotz.com> | 2021-10-14 12:20:03 +0100 |
| commit | fe06668f0de56635efe55310d7a64289a37c1d90 (patch) | |
| tree | 8b63e7453940109dc1bbccf97769fbe785106fce /src/hls/HTLPargen.v | |
| parent | fe42fed367f54b81021107473499465296db41c8 (diff) | |
| download | vericert-fe06668f0de56635efe55310d7a64289a37c1d90.tar.gz vericert-fe06668f0de56635efe55310d7a64289a37c1d90.zip | |
[sched] Fix passes with new predicates
Diffstat (limited to 'src/hls/HTLPargen.v')
| -rw-r--r-- | src/hls/HTLPargen.v | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/hls/HTLPargen.v b/src/hls/HTLPargen.v index 47e9467..64996c6 100644 --- a/src/hls/HTLPargen.v +++ b/src/hls/HTLPargen.v @@ -655,11 +655,12 @@ Definition add_control_instr_force (n : node) (st : stmnt) : mon unit := (AssocMap.set n st s.(st_controllogic))) (add_control_instr_force_state_incr s n st). - Fixpoint pred_expr (preg: reg) (p: pred_op) := match p with | Pvar pred => Vrange preg (Vlit (posToValue pred)) (Vlit (posToValue pred)) + | Ptrue => Vlit (ZToValue 1) + | Pfalse => Vlit (ZToValue 0) | Pnot pred => Vunop Vnot (pred_expr preg pred) | Pand p1 p2 => |