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| author | Yann Herklotz <git@yannherklotz.com> | 2021-03-02 10:27:33 +0000 |
|---|---|---|
| committer | Yann Herklotz <git@yannherklotz.com> | 2021-03-02 10:27:33 +0000 |
| commit | 05347ca5126f335b0479b71a4576b141e082fab5 (patch) | |
| tree | b4dc63f00ca3b8158ad11ea77fafd4cec382c95f /src/hls/HTLgen.v | |
| parent | 8ddf6a9ff669fbc28cb3247c6ce40cb8fa4cc3fc (diff) | |
| download | vericert-05347ca5126f335b0479b71a4576b141e082fab5.tar.gz vericert-05347ca5126f335b0479b71a4576b141e082fab5.zip | |
Add RAM to HTL
Diffstat (limited to 'src/hls/HTLgen.v')
| -rw-r--r-- | src/hls/HTLgen.v | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/hls/HTLgen.v b/src/hls/HTLgen.v index f1e6b2a..c071868 100644 --- a/src/hls/HTLgen.v +++ b/src/hls/HTLgen.v @@ -612,6 +612,7 @@ Definition transf_module (f: function) : mon HTL.module := clk current_state.(st_scldecls) current_state.(st_arrdecls) + None (conj (max_pc_wf _ LECTRL) (max_pc_wf _ LEDATA))) | _, _ => error (Errors.msg "More than 2^32 states.") end |