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author | Yann Herklotz <git@yannherklotz.com> | 2021-09-18 14:40:45 +0100 |
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committer | Yann Herklotz <git@yannherklotz.com> | 2021-09-18 14:40:45 +0100 |
commit | b666f88219893c82361606f8652297ecc7fb7a9f (patch) | |
tree | 946c2ddb5ce21b7af24ce6945fe5f83cbb274061 /src/hls/PrintVerilog.ml | |
parent | c4d44af5f3135aba4d4878f8f41c80d1f0b9e9a2 (diff) | |
parent | c4436c02648502c4cb327d2018229e62a2c0d1c0 (diff) | |
download | vericert-b666f88219893c82361606f8652297ecc7fb7a9f.tar.gz vericert-b666f88219893c82361606f8652297ecc7fb7a9f.zip |
Merge branch 'master' into develop
Diffstat (limited to 'src/hls/PrintVerilog.ml')
-rw-r--r-- | src/hls/PrintVerilog.ml | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/hls/PrintVerilog.ml b/src/hls/PrintVerilog.ml index a2700a1..a5fa554 100644 --- a/src/hls/PrintVerilog.ml +++ b/src/hls/PrintVerilog.ml @@ -75,7 +75,7 @@ let pprint_binop l r = let unop = function | Vneg -> " - " - | Vnot -> " ! " + | Vnot -> " ~ " let register a = match PMap.find_opt a !name_map with |