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authorYann Herklotz <git@yannherklotz.com>2021-03-02 10:26:34 +0000
committerYann Herklotz <git@yannherklotz.com>2021-03-02 10:26:34 +0000
commit5b2e88abeb23ac8b6e570e8c80422e3635088891 (patch)
tree1eb513b964a46035a6888a3e04cdfab4999590b2 /src/hls/PrintVerilog.ml
parenta2199f6bf69ae5cbbdb15227f8828b914baa4348 (diff)
downloadvericert-5b2e88abeb23ac8b6e570e8c80422e3635088891.tar.gz
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Add Verilog generation for rams
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