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author | Yann Herklotz <git@yannherklotz.com> | 2021-02-21 16:34:11 +0000 |
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committer | Yann Herklotz <git@yannherklotz.com> | 2021-02-21 16:34:11 +0000 |
commit | 85650692c13e8a3c9e377f8259059eef8712d3d3 (patch) | |
tree | 0598c865f308e9fc39b7a7bec6ab8a46ce48fdf9 /src/hls/PrintVerilog.ml | |
parent | 171b326ade18ab77eb155a9d203f2f523708b29b (diff) | |
parent | 71fee63bcd943d33c761f228227b1bf8c60c1aac (diff) | |
download | vericert-85650692c13e8a3c9e377f8259059eef8712d3d3.tar.gz vericert-85650692c13e8a3c9e377f8259059eef8712d3d3.zip |
Merge branch 'develop' into dev/divider
Diffstat (limited to 'src/hls/PrintVerilog.ml')
-rw-r--r-- | src/hls/PrintVerilog.ml | 17 |
1 files changed, 15 insertions, 2 deletions
diff --git a/src/hls/PrintVerilog.ml b/src/hls/PrintVerilog.ml index e9020ac..8c9f20e 100644 --- a/src/hls/PrintVerilog.ml +++ b/src/hls/PrintVerilog.ml @@ -192,6 +192,7 @@ let testbench = "module testbench; reg start, reset, clk; wire finish; wire [31:0] return_val; + reg [31:0] cycles; main m(start, reset, clk, finish, return_val); @@ -201,20 +202,23 @@ let testbench = "module testbench; reset = 0; @(posedge clk) reset = 1; @(posedge clk) reset = 0; + cycles = 0; end always #5 clk = ~clk; always @(posedge clk) begin if (finish == 1) begin + $display(\"cycles: %0d\", cycles); $display(\"finished: %0d\", return_val); $finish; end + cycles <= cycles + 1; end endmodule " -let debug_always i clk state = concat [ +let debug_always_verbose i clk state = concat [ indent i; "reg [31:0] count;\n"; indent i; "initial count = 0;\n"; indent i; "always @(posedge " ^ register clk ^ ") begin\n"; @@ -226,6 +230,15 @@ let debug_always i clk state = concat [ indent i; "end\n" ] +let debug_always i clk finish = concat [ + indent i; "reg [31:0] count;\n"; + indent i; "initial count = 0;\n"; + indent i; "always @(posedge " ^ register clk ^ ") begin\n"; + indent (i+2); "if(" ^ register finish ^ ") $display(\"Cycles: %0d\", count);\n"; + indent (i+1); "count <= count + 1;\n"; + indent i; "end\n" + ] + let print_initial i n stk = concat [ indent i; "integer i;\n"; indent i; "initial for(i = 0; i < "; sprintf "%d" n; "; i++)\n"; @@ -246,7 +259,7 @@ let pprint_module debug i n m = fold_map (pprint_module_item (i+1)) m.mod_body; concat (List.map (print_funct_units m.mod_clk) m.mod_funct_units); if !option_initial then print_initial i (Nat.to_int m.mod_stk_len) m.mod_stk else ""; - if debug then debug_always i m.mod_clk m.mod_st else ""; + if debug then debug_always_verbose i m.mod_clk m.mod_st else ""; indent i; "endmodule\n\n" ] else "" |