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authorYann Herklotz <git@yannherklotz.com>2021-03-01 11:05:12 +0000
committerYann Herklotz <git@yannherklotz.com>2021-03-01 11:05:12 +0000
commit975a5fb0c11af6e8db3f250322794c0712f4af90 (patch)
tree700cb068388ba30685c099f593dbd0bbcca29204 /src/hls/PrintVerilog.ml
parent5ba31274207ba24a15682f1aec9ad9e0f50e08ee (diff)
downloadvericert-975a5fb0c11af6e8db3f250322794c0712f4af90.tar.gz
vericert-975a5fb0c11af6e8db3f250322794c0712f4af90.zip
Change lists in case statements to stmnt_list
Diffstat (limited to 'src/hls/PrintVerilog.ml')
-rw-r--r--src/hls/PrintVerilog.ml4
1 files changed, 3 insertions, 1 deletions
diff --git a/src/hls/PrintVerilog.ml b/src/hls/PrintVerilog.ml
index aeaf75c..3817fd3 100644
--- a/src/hls/PrintVerilog.ml
+++ b/src/hls/PrintVerilog.ml
@@ -118,7 +118,9 @@ let rec pprint_stmnt i =
indent i; "end\n"
]
| Vcase (e, es, d) -> concat [ indent i; "case ("; pprint_expr e; ")\n";
- fold_map pprint_case (List.sort compare_expr es |> List.rev);
+ fold_map pprint_case (stmnt_to_list es
+ |> List.sort compare_expr
+ |> List.rev);
indent (i+1); "default:;\n";
indent i; "endcase\n"
]