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authorYann Herklotz <git@yannherklotz.com>2021-02-12 21:25:28 +0000
committerYann Herklotz <git@yannherklotz.com>2021-02-12 21:25:28 +0000
commit1db0826c5c72149fdba342b0773cc1705e17b49d (patch)
tree77f54d6612e5fce89012ba5866e48e6d90afa22b /src/hls/PrintVerilog.ml
parent23c4e482cad3aff97391f32b51993b053d6aa4db (diff)
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Add signed and unsigned division
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