diff options
| author | Michalis Pardalos <m.pardalos@gmail.com> | 2021-09-08 13:18:47 +0100 |
|---|---|---|
| committer | Michalis Pardalos <m.pardalos@gmail.com> | 2021-09-08 13:18:47 +0100 |
| commit | 9b7948bdb900e14e67b73520d98e8bbebec59286 (patch) | |
| tree | 0814b6aea6011236e9eb0ead9b72f869170816b7 /src/hls/PrintVerilog.mli | |
| parent | 25215f862dc8b768e16bfb86bd595947610af9f6 (diff) | |
| download | vericert-9b7948bdb900e14e67b73520d98e8bbebec59286.tar.gz vericert-9b7948bdb900e14e67b73520d98e8bbebec59286.zip | |
Print declarations in HTL output
Diffstat (limited to 'src/hls/PrintVerilog.mli')
| -rw-r--r-- | src/hls/PrintVerilog.mli | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/hls/PrintVerilog.mli b/src/hls/PrintVerilog.mli index dbb8ba0..6a996bd 100644 --- a/src/hls/PrintVerilog.mli +++ b/src/hls/PrintVerilog.mli @@ -25,3 +25,5 @@ val print_value : out_channel -> ValueInt.value -> unit val print_program : bool -> out_channel -> Verilog.program -> unit val print_result : out_channel -> (BinNums.positive * ValueInt.value) list -> unit + +val print_io : Verilog.io option -> (string * bool) |