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| author | Yann Herklotz <git@yannherklotz.com> | 2021-07-24 16:09:09 +0200 |
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| committer | Yann Herklotz <git@yannherklotz.com> | 2021-07-24 16:10:15 +0200 |
| commit | 0c021173b3efb1310370de4b2a6f5444c745022f (patch) | |
| tree | c1aeebc65a68d05f9de629f27f7e426035c263f7 /src/hls/Verilog.v | |
| parent | 3496f507d97547c8f544be8219768b000cadb840 (diff) | |
| download | vericert-0c021173b3efb1310370de4b2a6f5444c745022f.tar.gz vericert-0c021173b3efb1310370de4b2a6f5444c745022f.zip | |
Use main instead of top for synthesising Vericert designs
Diffstat (limited to 'src/hls/Verilog.v')
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