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| author | Yann Herklotz <git@yannherklotz.com> | 2021-03-03 21:12:15 +0000 |
|---|---|---|
| committer | Yann Herklotz <git@yannherklotz.com> | 2021-03-03 21:12:15 +0000 |
| commit | 57350a8ca5579b65978d7a723a20915e763a2d0b (patch) | |
| tree | dfcc0903de6e8994adee1b70eb7cc0e26fb12171 /src/hls/Veriloggen.v | |
| parent | ea14bf01e909d96590150c0f5271988b2bb2bf38 (diff) | |
| download | vericert-57350a8ca5579b65978d7a723a20915e763a2d0b.tar.gz vericert-57350a8ca5579b65978d7a723a20915e763a2d0b.zip | |
Add RAM semantics to HTL and fix proof
Diffstat (limited to 'src/hls/Veriloggen.v')
| -rw-r--r-- | src/hls/Veriloggen.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/hls/Veriloggen.v b/src/hls/Veriloggen.v index cf36d27..3defe9c 100644 --- a/src/hls/Veriloggen.v +++ b/src/hls/Veriloggen.v @@ -52,7 +52,7 @@ Definition transl_module (m : HTL.module) : Verilog.module := let case_el_ctrl := list_to_stmnt (transl_list (PTree.elements m.(mod_controllogic))) in let case_el_data := list_to_stmnt (transl_list (PTree.elements m.(mod_datapath))) in match m.(HTL.mod_ram) with - | Some (addr, d_in, d_out, wr_en) => + | Some (mk_ram ram addr wr_en d_in d_out) => let body := Valways (Vposedge m.(HTL.mod_clk)) (Vcond (Vbinop Veq (Vvar m.(HTL.mod_reset)) (Vlit (ZToValue 1))) (Vnonblock (Vvar m.(HTL.mod_st)) (Vlit (posToValue m.(HTL.mod_entrypoint)))) |