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| author | Yann Herklotz <git@yannherklotz.com> | 2021-03-01 11:05:12 +0000 |
|---|---|---|
| committer | Yann Herklotz <git@yannherklotz.com> | 2021-03-01 11:05:12 +0000 |
| commit | 975a5fb0c11af6e8db3f250322794c0712f4af90 (patch) | |
| tree | 700cb068388ba30685c099f593dbd0bbcca29204 /src/hls/Veriloggen.v | |
| parent | 5ba31274207ba24a15682f1aec9ad9e0f50e08ee (diff) | |
| download | vericert-975a5fb0c11af6e8db3f250322794c0712f4af90.tar.gz vericert-975a5fb0c11af6e8db3f250322794c0712f4af90.zip | |
Change lists in case statements to stmnt_list
Diffstat (limited to 'src/hls/Veriloggen.v')
| -rw-r--r-- | src/hls/Veriloggen.v | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/hls/Veriloggen.v b/src/hls/Veriloggen.v index 80c0669..894d309 100644 --- a/src/hls/Veriloggen.v +++ b/src/hls/Veriloggen.v @@ -43,8 +43,8 @@ Definition arr_to_Vdeclarr_fun (a : reg * (option io * arr_decl)) := Definition arr_to_Vdeclarr arrdecl := map arr_to_Vdeclarr_fun arrdecl. Definition transl_module (m : HTL.module) : Verilog.module := - let case_el_ctrl := transl_list (PTree.elements m.(mod_controllogic)) in - let case_el_data := transl_list (PTree.elements m.(mod_datapath)) in + let case_el_ctrl := list_to_stmnt (transl_list (PTree.elements m.(mod_controllogic))) in + let case_el_data := list_to_stmnt (transl_list (PTree.elements m.(mod_datapath))) in let body := Valways (Vposedge m.(HTL.mod_clk)) (Vcond (Vbinop Veq (Vvar m.(HTL.mod_reset)) (Vlit (ZToValue 1))) (Vnonblock (Vvar m.(HTL.mod_st)) (Vlit (posToValue m.(HTL.mod_entrypoint)))) |