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| author | Michalis Pardalos <m.pardalos@gmail.com> | 2021-08-26 19:27:17 +0100 |
|---|---|---|
| committer | Michalis Pardalos <m.pardalos@gmail.com> | 2021-08-26 19:27:17 +0100 |
| commit | b067e5c7b0ecce9ffbf21e9c4a7ff96328dec2ba (patch) | |
| tree | d36a28e84827fe0bb8d7b87d9afa8475b7b2008e /src/hls/Veriloggen.v | |
| parent | 4dca6dbd48d3e71eb550297d3325555f5e039bb8 (diff) | |
| parent | 0c021173b3efb1310370de4b2a6f5444c745022f (diff) | |
| download | vericert-b067e5c7b0ecce9ffbf21e9c4a7ff96328dec2ba.tar.gz vericert-b067e5c7b0ecce9ffbf21e9c4a7ff96328dec2ba.zip | |
Merge branch 'oopsla21' into sharing-merge
Diffstat (limited to 'src/hls/Veriloggen.v')
| -rw-r--r-- | src/hls/Veriloggen.v | 41 |
1 files changed, 30 insertions, 11 deletions
diff --git a/src/hls/Veriloggen.v b/src/hls/Veriloggen.v index 7ace6be..1ded68a 100644 --- a/src/hls/Veriloggen.v +++ b/src/hls/Veriloggen.v @@ -62,6 +62,9 @@ Section TRANSLATE. | _ => Some it end. + Definition mod_body (m : HTL.module) := + + (* FIXME Remove the fuel parameter (recursion limit)*) Fixpoint transl_module (fuel : nat) (prog : HTL.program) (externclk : option reg) (m : HTL.module) : res Verilog.module := match fuel with @@ -99,17 +102,33 @@ Section TRANSLATE. let local_scldecls := PTree.filter (fun r _ => negb (PTree.contains r externctrl)) (HTL.mod_scldecls m) in let scl_decls := scl_to_Vdecls (AssocMap.elements local_scldecls) in - let body : list Verilog.module_item:= - Valways (Vposedge clk) (Vcond (Vbinop Veq (Vvar (HTL.mod_reset m)) (Vlit (ZToValue 1))) - (Vseq - (Vnonblock (Vvar (HTL.mod_st m)) (Vlit (posToValue (HTL.mod_entrypoint m)))) - (Vnonblock (Vvar (HTL.mod_finish m)) (Vlit (ZToValue 0)))) - (Vcase (Vvar (HTL.mod_st m)) case_el_ctrl (Some Vskip))) - :: Valways (Vposedge clk) (Vcase (Vvar (HTL.mod_st m)) case_el_data (Some Vskip)) - :: arr_decls - ++ scl_decls - ++ maybe_clk_decl - ++ List.flat_map Verilog.mod_body (List.map snd (PTree.elements cleaned_modules)) in + let body : list Verilog.module_item := + match (HTL.mod_ram m) with + | Some ram => + Valways (Vposedge clk) (Vcond (Vbinop Veq (Vvar (HTL.mod_reset m)) (Vlit (ZToValue 1))) + (Vseq + (Vnonblock (Vvar (HTL.mod_st m)) (Vlit (posToValue (HTL.mod_entrypoint m)))) + (Vnonblock (Vvar (HTL.mod_finish m)) (Vlit (ZToValue 0)))) + (Vcase (Vvar (HTL.mod_st m)) case_el_ctrl (Some Vskip))) + :: Valways (Vposedge clk) (Vcase (Vvar (HTL.mod_st m)) case_el_data (Some Vskip)) + :: inst_ram m.(HTL.mod_clk) ram + :: arr_decls + ++ scl_decls + ++ maybe_clk_decl + ++ List.flat_map Verilog.mod_body (List.map snd (PTree.elements cleaned_modules)) + | Nothing => + Valways (Vposedge clk) (Vcond (Vbinop Veq (Vvar (HTL.mod_reset m)) (Vlit (ZToValue 1))) + (Vseq + (Vnonblock (Vvar (HTL.mod_st m)) (Vlit (posToValue (HTL.mod_entrypoint m)))) + (Vnonblock (Vvar (HTL.mod_finish m)) (Vlit (ZToValue 0)))) + (Vcase (Vvar (HTL.mod_st m)) case_el_ctrl (Some Vskip))) + :: Valways (Vposedge clk) (Vcase (Vvar (HTL.mod_st m)) case_el_data (Some Vskip)) + :: arr_decls + ++ scl_decls + ++ maybe_clk_decl + ++ List.flat_map Verilog.mod_body (List.map snd (PTree.elements cleaned_modules)) + end + in OK (Verilog.mkmodule (HTL.mod_start m) |