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| author | Yann Herklotz <git@yannherklotz.com> | 2020-11-02 19:38:43 +0000 |
|---|---|---|
| committer | Yann Herklotz <git@yannherklotz.com> | 2020-11-02 19:38:43 +0000 |
| commit | 0237b9d05778b825bc56562aa2ba3b7bd351af14 (patch) | |
| tree | 580a0823acadf68ce2621137592e01178be1bde4 /src/hls | |
| parent | 32cfca30754f13cd91b228712cd65d3115a3f355 (diff) | |
| download | vericert-0237b9d05778b825bc56562aa2ba3b7bd351af14.tar.gz vericert-0237b9d05778b825bc56562aa2ba3b7bd351af14.zip | |
Fix pretty printing bug in Verilog
Diffstat (limited to 'src/hls')
| -rw-r--r-- | src/hls/PrintVerilog.ml | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/hls/PrintVerilog.ml b/src/hls/PrintVerilog.ml index 353bfac..44710b8 100644 --- a/src/hls/PrintVerilog.ml +++ b/src/hls/PrintVerilog.ml @@ -65,7 +65,7 @@ let pprint_binop l r = | Vshru -> unsigned ">>" let unop = function - | Vneg -> " ~ " + | Vneg -> " - " | Vnot -> " ! " let register a = sprintf "reg_%d" (P.to_int a) @@ -177,7 +177,7 @@ let testbench = "module testbench; always @(posedge clk) begin if (finish == 1) begin - $display(\"finished: %d\", return_val); + $display(\"finished: %0d\", return_val); $finish; end end |