diff options
author | James Pollard <james@pollard.dev> | 2020-06-24 20:09:13 +0100 |
---|---|---|
committer | James Pollard <james@pollard.dev> | 2020-06-24 20:09:13 +0100 |
commit | bb80bc5d196665498f7b365e9e26468ed5999ea9 (patch) | |
tree | 8de28c77930806c0cbb1719b66bdb68463b45937 /src/translation/HTLgen.v | |
parent | c31d0037ba769f99f45edf3c02c82a71414a8d25 (diff) | |
download | vericert-bb80bc5d196665498f7b365e9e26468ed5999ea9.tar.gz vericert-bb80bc5d196665498f7b365e9e26468ed5999ea9.zip |
HTLgenproof passing.
Diffstat (limited to 'src/translation/HTLgen.v')
-rw-r--r-- | src/translation/HTLgen.v | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/src/translation/HTLgen.v b/src/translation/HTLgen.v index e637d6f..54ad77a 100644 --- a/src/translation/HTLgen.v +++ b/src/translation/HTLgen.v @@ -395,10 +395,6 @@ Definition translate_arr_access (mem : AST.memory_chunk) (addr : Op.addressing) if (check_address_parameter off) then ret (Vvari stack (Vbinop Vdiv (boplitz Vadd r1 off) (Vlit (ZToValue 32 4)))) else error (Errors.msg "HTLgen: translate_arr_access address misaligned") - | Mint32, Op.Ascaled scale offset, r1::nil => - if (check_address_parameter scale) && (check_address_parameter offset) - then ret (Vvari stack (Vbinop Vdiv (Vbinop Vadd (boplitz Vmul r1 scale) (Vlit (ZToValue 32 offset))) (Vlit (ZToValue 32 4)))) - else error (Errors.msg "HTLgen: translate_arr_access address misaligned") | Mint32, Op.Aindexed2scaled scale offset, r1::r2::nil => (* Typical for dynamic array addressing *) if (check_address_parameter scale) && (check_address_parameter offset) then ret (Vvari stack |