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author | Yann Herklotz <git@yannherklotz.com> | 2020-06-12 11:38:14 +0100 |
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committer | Yann Herklotz <git@yannherklotz.com> | 2020-06-12 11:38:14 +0100 |
commit | 7ad63f341fe3c28ef20bfde755bdf21403077504 (patch) | |
tree | 88e57998e5ffaec6727baf99eff9fb0c5220d375 /src/translation/Veriloggenproof.v | |
parent | 13b880f99b7355010551ad1b93242cf7773aa202 (diff) | |
download | vericert-7ad63f341fe3c28ef20bfde755bdf21403077504.tar.gz vericert-7ad63f341fe3c28ef20bfde755bdf21403077504.zip |
Remove Verilog proofs
Diffstat (limited to 'src/translation/Veriloggenproof.v')
-rw-r--r-- | src/translation/Veriloggenproof.v | 23 |
1 files changed, 4 insertions, 19 deletions
diff --git a/src/translation/Veriloggenproof.v b/src/translation/Veriloggenproof.v index 942a83a..6c58c56 100644 --- a/src/translation/Veriloggenproof.v +++ b/src/translation/Veriloggenproof.v @@ -17,30 +17,15 @@ *) From compcert Require Import Smallstep. -From compcert Require RTL. -From coqup Require Verilog. +From coqup Require HTL Verilog. Section CORRECTNESS. - Variable prog: RTL.program. - Variable tprog: Verilog.module. - - Inductive match_states: RTL.state -> Verilog.state -> Prop := - | match_state: - forall, - - match_states (RTL.State f s k sp e m) - (Verilog.State m mi mis assoc nbassoc f cycle pc) - | match_returnstate: - forall v tv k m tm cs - (MS: match_stacks k cs) - (LD: Val.lessdef v tv) - (MEXT: Mem.extends m tm), - match_states (CminorSel.Returnstate v k m) - (RTL.Returnstate cs tv tm). + Variable prog: HTL.program. + Variable tprog: Verilog.program. Theorem transf_program_correct: - forward_simulation (RTL.semantics prog) (Verilog.semantics tprog). + forward_simulation (HTL.semantics prog) (Verilog.semantics tprog). Admitted. End CORRECTNESS. |